
subckt HalfCell out in BL WL VDD VSS 
parameters vt0=0 vt1=0 vt2=0
MN (out G0 VSS VSS) NMOS_VTL w=90n l=50n 
MP (out G1 VDD VDD) PMOS_VTL w=90n l=50n 

MT (BL G2 out VSS ) NMOS_VTL w=110n l=50n 
 
V0 (in G0) vsource dc=vt0 type=dc
V1 (in G1) vsource dc=vt1 type=dc
V2 (WL G2) vsource dc=vt2 type=dc
ends HalfCell

//============================================
// 6T Bitcell
//============================================
subckt BITCELL (BL BLB WL VDD  VSS)
parameters vt0=0 vt1=0 vt2=0 vt3=0 vt4=0 vt5=0
  ICellLh (Q QB BL WL VDD  VSS HalfCell vt0=pvt0 vt1=pvt1 vt2=pvt2
  ICellRh (QB Q BLB WL VDD  VSS) HalfCell vt0=pvt3 vt1=pvt4 vt2=pvt5
ends BITCELL

subckt BITCELL8T (BL BLB WL RWL RBL VDD  VSS)
parameters vt0=0 vt1=0 vt2=0 vt3=0 vt4=0 vt5=0 vt6=0 vt7=0
  ICellLh (Q QB BL WL VDD  VSS HalfCell vt0=pvt0 vt1=pvt1 vt2=pvt2
  ICellRh (QB Q BLB WL VDD  VSS) HalfCell vt0=pvt3 vt1=pvt4 vt2=pvt5

MRA (RBL G0 INT VSS) NMOS_VTL w=90n l=50n 
MRP (INT G1 VSS VSS) NMOS_VTL w=90n l=50n 
V0 (RWL G0) vsource dc=vt6 type=dc
V1 (QB  G1) vsource dc=vt7 type=dc

ends BITCELL8T


ICell0 (BL BLB WL VDD VSS) BITCELL vt0=pvt0 vt1=pvt1 vt2=pvt2 vt3=pvt3 vt4=pvt4 vt5=pvt5

VVDD (VDD 0) vsource dc=pvdd
VVSS (VSS 0) vsource dc=0

VBL (BL 0) vsource dc=pvbl
VBLB (BLB 0) vsource dc=pvblb

// sweep WL
VVIN (WL 0) vsource dc=pvin

